A content addressable memory (CAM) is a memory wherein a stored element is identified on the basis of data content rather than on storage address location. A CAM is generally formed of CAM cells arranged in rows and columns to form an array. In a traditional CAM array architecture, information is typically accessed simultaneously and in parallel to provide a data processing system which completes a large number of operations in a relatively short amount of time. The unique architecture of the CAM array has found applications in many data processing systems. For example, the parallel processing of the CAM array enables a significant amount of data from memory to be retrieved from a data processing system in less time than a conventional memory implementation. In more advanced applications, the CAM array also enables the user to expand the memory addresses of the system with no added internal memory space or added memory access time. The simple parallel operation and fast memory access times enable the CAM array to be used in a variety of applications which are not limited to accessing information from memory.
The parallel operation of the CAM array is readily implemented in a data processing system. During typical operation of the CAM array, current information loaded in the CAM array is generally referred to as the TAG word and information previously stored in the CAM array is generally referred to as a stored word. The TAG word is defined by the user of the data processing system and is compared with a plurality of stored words which have previously been stored in a CAM array. In a masked CAM array, only a portion of the bits in the stored words participate in a comparison with a similar portion of bits in the TAG word. In both cases, the TAG word and the array of stored words are simultaneously compared in parallel. If the TAG word is identical to a stored word, the CAM array provides an output signal which indicates whether or not a match occurred. Because the comparison of the TAG word with the array of stored words occurs throughout the entire array simultaneously, the memory access time of the CAM array is significantly reduced from that of a traditional memory which is used to implement the same function.
Although CAM arrays access data more quickly than other memory devices, certain characteristics detract from their performance. For example, in certain systems, if two or more matches are observed between the TAG word and the stored words in the CAM array, an incorrect output signal is provided to the data processing system. Assume that the CAM array is implemented as an address translator for providing addresses to a random access memory (RAM). If two or more matches occur during a comparison between the TAG word and the stored words in the CAM array, the CAM array provides two or more output signals to corresponding differing locations in the RAM. Therefore, if the output signals are provided to read the RAM, two or more memory locations are accessed and the resultant data on the data bus is corrupted.
Generally, two or more match signals are asserted when the TAG word matches two or more stored words in the CAM array. Some content addressable memory systems detect the occurrence of two or more match signals by using a significant amount of additional logic circuitry. After two or more match signals occur, the data processing system provides a solution to the conflict. The data processing system may implement either a prioritization routine which enables only a match signal with a highest priority level or a logic circuit which disables all asserted match signals and clears the contents of the corresponding cells in the CAM array. In either case, the added circuitry results in added memory access time as well as a significant number of added components to the data processing system.